/* CONSTANTS REQUIRED BY THIS DRIVER */ /* DEVICE STATES */ #define CLOSED 0x0000 /* DEVICE IS CLOSED */ #define TIMEOUT 0x0001 /* A TIMEOUT HAS OCCURRED */ #define OPEN 0x0002 /* DEVICE IS CURRENTLY OPEN */ #define HOST_BLOCKED 0x0004 /* WE HAVE BLOCKED THE REMOTE SYSTEM */ #define WE_ARE_BLOCKED 0x0008 /* OUR OUTPUT IS BLOCKED BY AN XOFF */ #define BLOCK_HOST 0x0010 /* SEND AN XOFF */ #define UNBLOCK_HOST 0x0020 /* SEND AN XON */ #define SEND_ACK 0x0040 /* SEND AN ACK */ #define CARRIER 0x0080 /* CARRIER HAS BEEN DETECTED */ #define SLEEP 0x0100 /* DEVICE IS ASLEEP, WAITING FOR INPUT */ #define READ_ACCESS 0x0200 /* DEVICE IS OPEN FOR READ ACCESS */ #define WRITE_ACCESS 0x0400 /* DEVICE IS OPEN FOR WRITE ACCESS */ #define NO_DELAY 0x0800 /* DEVICE IS OPEN FOR NON-BLOCKING I/O */ #define A_READ_TIMEOUT 0x1000 /* A READ TIMEOUT OCCURRED */ #define RESET_MASK 0x0E82 /* MASK USED WHEN RESET PERFORMED */ /* HANDSHAKE CHARACTERS */ #define XON 17 #define XOFF 19 #define ENQ 5 #define ACK 6 /* TIMEOUT ID NUMBERS */ #define READ 1 #define MISC 0 /* ERROR EQUATES */ #define NO_ERROR 0 #define INVALID_OP 1 #define INVALID_PARM 2 #define READ_ONLY 3 #define WRITE_ONLY 4 #define SELFTEST 5 #define NO_CARRIER 6 #define INVALID_COUNT 7 #define XMITER_DISABLED 8 #define READ_TIMEOUT_ERR 9 /* ACCESS OPTIONS */ #define O_RDONLY 0 #define O_WRONLY 1 #define O_RDWR 2 #define O_NDELAY 4 /* PROCEDURE RETURN STATUS */ #define NON_IFACE_ERROR (-2) /* NON-INTERFACE SPECIFIC ERROR */ #define IFACE_ERROR (-1) /* INTERFACE SPECIFIC ERROR */ /* STATUS RETURNED BY Output() PROCEDURE */ #define NO_BUF_CHAR_SENT 0 #define BUF_CHAR_SENT 1 /* LOGICAL REGISTER EQUATES */ #define ERROR_REG 0 #define CONTROL_LINES 1 #define EVENT_INDICATOR 2 #define INTR_EVENT_MASK 3 #define INTR_EVENT_INDICATOR 4 #define TIMEOUT_EVENT_MASK 5 #define TIMEOUT_EVENT_INDICATOR 6 #define XFER_EVENT_MASK 7 #define XFER_EVENT_INDICATOR 8 #define STATUS_LINES 9 #define XMITTER_RECVR_STATUS 10 #define HANDSHAKE 11 #define LINE_CHAR 12 #define PARITY 13 #define BAUD_MSB 14 #define BAUD_LSB 15 #define PARITY_CHAR 16 #define FRAMING_CHAR 17 #define READ_TIMEOUT_B1 18 #define READ_TIMEOUT_B2 19 #define READ_TIMEOUT_B3 20 #define READ_TIMEOUT_B4 21 #define IO_TERM_CHAR_1 22 #define IO_TERM_CHAR_2 23 #define IO_TERM_CHAR_3 24 #define IO_TERM_CHAR_4 25 /* LOGICAL REGISTER 1 */ #define DTR_LINE 0x01 #define RTS_LINE 0x02 #define DRS_LINE 0x08 /* LOGICAL REGISTER 2 */ #define INTR_EVENT 0x01 #define TRNSFR_EVENT 0x02 #define TIMEOUT_EVENT 0x04 /* LOGICAL REGISTER 3 */ #define ALLOW_CTS_EVENT 0x01 #define ALLOW_DSR_EVENT 0x02 #define ALLOW_RI_EVENT 0x04 #define ALLOW_DCD_EVENT 0x08 #define ALLOW_BUFFER_OVERRUN_EVENT 0x10 #define ALLOW_PARITY_ERROR_EVENT 0x20 #define ALLOW_FRAMING_ERROR_EVENT 0x40 #define ALLOW_BREAK_RCVD_EVENT 0x80 /* LOGICAL REGISTER 4 */ #define CTS_EVENT 0x01 #define DSR_EVENT 0x02 #define RI_EVENT 0x04 #define DCD_EVENT 0x08 #define BUFFER_OVERRUN_EVENT 0x10 #define PARITY_ERROR_EVENT 0x20 #define FRAMING_ERROR_EVENT 0x40 #define BREAK_RCVD_EVENT 0x80 /* LOGICAL REGISTER 5 & 6 */ #define READ_TIMEOUT 0x01 /* LOGICAL REGISTER 7 */ #define ALLOW_CR22_EVENT 0x01 #define ALLOW_CR23_EVENT 0x02 #define ALLOW_CR24_EVENT 0x04 #define ALLOW_CR25_EVENT 0x08 /* LOGICAL REGISTER 8 */ #define CR22_RECVD 0x01 #define CR23_RECVD 0x02 #define CR24_RECVD 0x04 #define CR25_RECVD 0x08 /* LOGICAL REGISTER 10 */ #define RECVR_ENABLED 0x01 #define XMITER_ENABLED 0x02 #define OPERATION_MODE 0x0C #define RX_CONTROL 0x10 #define TX_CONTROL 0x20 #define IGNORE_CARRIER 0x40 #define ENABLE_BREAK 0x80 /* LOGICAL REGISTER 11 */ #define XMIT_PACING_MODE 0x03 #define RECV_PACING 0x04 #define ENQ_ACK_HNDSHKE 0x08 /* LOGICAL REGISTER 12 */ #define DATA_BITS 0x03 #define STOP_BITS 0x3C /* LOGICAL REGISTER 13 */ #define PARITY_MODE 0x03 #define PARITY_TYPE 0x04 /* IOCTL COMMANDS */ #define SERIAL_FLUSH_BUF (('s'<<8)|0) #define SERIAL_BREAK (('s'<<8)|1) #define MAX_DEVICES 32 /* MAX # OF DEVICES IN SYSTEM */ /* MISC EQUATES */ #define NUM_OF_LOGICAL_REGISTERS 26 #define FLUSH_IN_BUF 0x00 #define FLUSH_OUT_BUF 0x01 #define FLUSH_BOTH 0x02 #define INITIAL_INTR_MASK 0x86 #define SELFTEST_TIME_LIMIT 5000 #define BREAK_LEN 200 #define BUF_SIZE 257 #define RW_ACCESS 0x03 #define OFLAG_MASK 0xFFF8 #define THRESHOLD BUF_SIZE/2 #define TRUE 1 #define FALSE 0 #define PRIORITY 0 /* PHYSICAL REGISTER EQUATES */ #define ENABLE_INTR 0x80 /* Channel_A_Command_Register */ #define ENABLE_RECEIVER 0x01 #define DISABLE_RECEIVER 0x02 #define ENABLE_XMITER 0x04 #define DISABLE_XMITER 0x08 #define NO_COMMAND 0x00 #define RESET_MR_PTR 0x10 #define RESET_RECEIVER 0x20 #define RESET_XMITTER 0x30 #define RESET_ERROR_STAT 0x40 #define RESET_BREAK_INDICATOR 0x50 #define SEND_BREAK 0x60 #define STOP_BREAK 0x70 /* MISC HARDWARE REGISTERS */ #define AUX_CMD 0x6F #define OUT_PORT_CONFIG 0x02 #define OUT_PORT_MASK 0x0B #define CLOCK_SELECT 0xDD /* INTERRUPT MASK & INTERRUPT CAUSE REGISTERS */ #define TxRDY 0x01 #define RxRDY 0x02 #define DELTA_BREAK 0x04 #define IN_PORT_CHANGE 0x80 /* Channel_A_Status_Register */ #define RECV_ERROR 0xF0 #define RECV_BREAK 0x80 #define RECV_FRAME_ERROR 0x40 #define RECV_PARITY_ERROR 0x20 #define RECV_OVERRUN_ERROR 0x10 #define XMIT_REG_EMPTY 0x04 #define RECV_READY 0x01 /* Input_Port_Change_Register */ #define DELTA_DCD 0x80 #define DELTA_RI 0x40 #define DELTA_DSR 0x20 #define DELTA_CTS 0x10 #define DCD_LOW 0x08 #define RI_LOW 0x04 #define DSR_LOW 0x02 #define CTS_LOW 0x01 /* #define port(mdev) (((mdev) & 0x00FF0000) >> 16) */ #define port(mdev) (16) #define port_to_base(port_num) (0x0E0000) #define base_to_port(base) (16) #define make_dev(port) ((port & 0x000000FF) << 16) /* GLOBAL DATA STRUCTURES REQUIRED BY THE SERIAL INTERFACE DRIVER */ struct serial_globals { char input_buf[BUF_SIZE]; /* 256 BYTE INPUT BUFFER */ int input_fill_ptr; /* FILL PTR FOR INPUT BUFFER */ int input_empty_ptr; /* EMPTY PTR FOR INPUT BUFFER */ char output_buf[BUF_SIZE]; /* 256 BYTE OUTPUT BUFFER */ int output_fill_ptr; /* FILL PTR FOR OUTPUT BUFFER */ int output_empty_ptr; /* EMPTY PTR FOR OUTPUT BUFFER */ char status_register[NUM_OF_LOGICAL_REGISTERS]; /* 26 LOGICAL REGS */ int sleep_byte_count; /* # OF INPUT BYTES NEEDED TO WAKE */ /* A SLEEPING PROCESS. */ int sleep_timeout; /* TIMEOUT ID FOR SLEEPING PROCESS */ char intr_mask; /* CURRENT HARDWARE INTERRUPT MASK */ }; struct serial_globals ser_globs; struct serial_globals *globals = &ser_globs; long device_state; /* CURRENT STATE OF EACH DEVICE */ /* CONTROLLED BY THIS DRIVER */ /* BELOW IS THE STRUCTURE DESCRIBING THE PHYSICAL REGISTER LAYOUT */ struct registers { char byte0, Status_ID_Register, byte2, byte3, byte4, byte5, byte6, byte7, byte8, byte9, byte10, byte11, byte12, byte13, byte14, byte15, byte16, byte17, byte18, byte19, byte20, byte21, byte22, byte23, byte24, byte25, byte26, byte27, byte28, byte29, byte30, byte31, byte32, byte33, byte34, Output_Port_Configuration_Register, byte36, Set_Output_Port_Register, byte38, Reset_Output_Port_Register, byte40, Channel_B_Mode_Register, byte42, Channel_B_Clock_Select_Register, byte44, Channel_B_Command_Register, byte46, Transfer_Register_B, byte48, Auxiliary_Command_Register, byte50, Interrupt_Mask_Register, byte52, Timer_Upper_Register, byte54, Timer_Lower_Register, byte56, Channel_A_Mode_Register, byte58, Channel_A_Clock_Select_Register, byte60, Channel_A_Command_Register, byte62, Data_Transfer_Register_A }; #define Channel_A_Status_Register Channel_A_Clock_Select_Register #define Input_Port_Register Output_Port_Configuration_Register #define Interrupt_Cause_Register Interrupt_Mask_Register #define Input_Port_Change_Register Auxiliary_Command_Register struct csdata { short regnum; short regcnt; char *data; }; struct timeout_blk { long dev; int to_num; }; struct init_data { long in_dev [MAX_DEVICES]; long out_dev [MAX_DEVICES]; }; struct driver_info { int id; int type; }; union ioctl_data { int int_value; char *ptr; }