/* memory map register addresses */
   
#define	MMAP 	0x650000
#define	MCTRL	(MMAP+0x1000)
#define	PNUMREG	(MMAP+0x3000)
#define	MPERROR	(MMAP+0x4000)

/* memory map control register values */

#define MM_CTL	0x1		/* mmgt ctl on */
#define MM_AVE	0x2		/* access violation enable */
#define MM_PEE	0x4		/* parity error enable */
#define MM_TME	0x8		/* timeout enable */
#define	MM_INT	0xFF		/* mmgt and interrupts on	*/

/* memory map error register values */

#define SEGMENT_ERROR	1	/* segmentation error */
#define TIMEOUT_ERROR	2	/* bus timeout error */
#define PARITY_ERROR	4	/* Memory parity error */

/* access abilities */

#define	PG_UR	0x00400000	/* user read */
#define	PG_UW	0x00200000	/* user write */
#define	PG_KR	0x00100000	/* supervisor read */
#define	PG_KW	0x00080000	/* supervisor write */
#define	PG_UKR	(PG_UR+PG_KR)	/* supervisor/user read */
#define	PG_UKW	(PG_UW+PG_KW)	/* supervisor/user write */

/* page table entry masks */

#define	PG_PN	0xFF000000	/* process number mask */
#define	PG_DB 	0x00800000	/* dirty bit mask */
#define	PG_PROT	0x00780000	/* access mask */
#define	PG_PFNUM 0x00003FFF	/* physical page number mask */

/* shift counts and masks */

#define PAGESHFT 10		/* 1024 = 2 ** 10 */
#define PAGEDISP 0x3ff		/* 10 bits of offset in page */
#define PAGENUM  0x3ff		/* page number mask after >> PAGESHFT */
#define MAXVIRT	 0x3ff		/* max possible virt address (clicks) */


/* page table entry structure */

struct pt_entry {
	int pg_pnum : 8;
	int pg_dirty : 1;
	int pg_prot : 4;
	int pg_unused : 5;
	int pg_pfnum : 14;
};

/* defines for expansion of user virtual space */

#define	DATASEG	0		/* user code and data segment */
#define STACKSEG 1		/* user stack segment */