/* Machine dependent information for 68000 system */

#define NPAGES 1024		/* number of pages in pagetbl */

/* Status bits:							*/

#define	S_TRACE	0x8000		/* Trace enabled		*/
#define	S_PMASK	0x0700		/* Priority mask		*/
#define	S_PRONE	0x0100		/* Priority level one.		*/
#define	S_SUPER	0x2000		/* Super-mode enabled		*/

#define	MMAP	0x650000	/* Memory map location		*/
#define	MCTRL	(MMAP+0x1000)	/* Control word location	*/
#define MM_CTL	0x1		/* mmgt ctl on */
#define MM_AVE	0x2		/* access violation enable */
#define MM_PEE	0x4		/* parity error enable */
#define MM_TME	0x8		/* timeout enable */

#define PNUMREG	(MMAP+0x3000)	/* process number for mmap	*/
#define PERROR	(MMAP+0x4000)	/* Error register */
#define SEGMENT_ERROR	1	/* segmentation error */
#define TIMEOUT_ERROR	2	/* bus timeout error */
#define PARITY_ERROR	4	/* Memory parity error */

#define	INTON	0xFF		/* mmgt and interrupts on	*/
#define	PAGES	1024		/* Number of pages		*/
#define	PSIZE	10		/* Number of bits in page offset*/

#define RAM	0xE0000		/* start of system RAM */
#define BOOTSIZ 0x2000		/* size of boot rom (starts at 0) */

/* describes:
     31: msb
     31-24  :  process id
     23     :  dirty
     22-21  :  read/write user
     20-19  :  read/write system
     18-0   :  mapped address
     0: lsb
*/

union map_word		/* details of 68000 page map entries */
{
	long map_long_form;
	struct
	{
		int map_high_part:3;
		int map_access:4;
		int map_dirty:1;
		int map_pnum:8;
		int map_low_part:16;
	} map_detail;
};

typedef union map_word page_tbl[NPAGES];

/* flags for access field */

#define M_SYS_W 1
#define M_SYS_R 2
#define M_USR_W 4
#define M_USR_R 8

#define NVECS 46

/* describes the pseudo interrupts in high RAM */
struct pseudo_i {
	short	i_op;
	long	i_adrs;
};