/* clock registers */

#define	CLK_BASE   0x657021		/* start of clock registers */
#define	CLK_CNTL   0x00			/* clock control reg offset */
#define	CLK_PLOD   0x04			/* clock preload reg offset */
#define	CLK_CNTR   0x0C			/* clock counter reg offset */
#define	CLK_STAT   0x14			/* clock status reg offset */

#define	CLK_ENAB   0xE5    		/* clock enable */
#define	CLK_DISA   0xE4			/* clock disable */
#define	CLK_INIT   0x500		/* clock preload value (60 HZ) */